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2012/08/31(Fri)

System Generator¤ÈSimulink¤ò¾¯¤·»È¤Ã¤Æ¤ß¤Æ

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2012/08/28(Tue)

Digilent¼ÒÀ½USB-JTAG¥±¡¼¥Ö¥ë

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2012/08/23(Thu)

VGA½ÐÎÏÀ®¸ù

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2012/08/09(Thu)

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  • ÅëºÜFPGA : Spartan-6 XC6SLX150
  • ¥Ü¡¼¥É : ¥Ò¥å¡¼¥Þ¥ó¥Ç¡¼¥¿À½XCM-110B
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¤È¤ê¤¢¤¨¤ºSpartan-6¥Ü¡¼¥É¾å¤ÎLED¤È¥¹¥¤¥Ã¥Á¤ò»È¤Ã¤Æ´Êñ¤ÊÆþ½ÐÎϤÎHDL¤È¥¯¥í¥Ã¥¯Ê¬¼þ¡ÜLED½ÐÎϤÎHDL¤ò½ñ¤¤¤¿¤È¤³¤íÀµ¾ï¤ËÆ°ºî¤µ¤»¤ë¤³¤È¤¬¤Ç¤­¤¿¡£

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This device supports attached Flash PROMs.
Do you want to attach an SPI or BPI PROM to this device?

WARNING:Xst:1710¤È1895

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WARNING:Xst:1710 - FF/Latch <cnt_24> (without init value) has a constant value of 0 in block <spartan6tes120809>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cnt_25> (without init value) has a constant value of 0 in block <spartan6tes120809>. This FF/Latch will be trimmed during the optimization process.

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WARNING:HDLCompiler:413 - "C:\programming\xilinx\spartan6tes120809\spartan6tes120809.v" Line 42: Result of 25-bit expression is truncated to fit in 24-bit target.

ÅÓÃæ¤Ç25bitÉý¤Î·×»»¤¹¤ë¤±¤É¡¢¾å°Ì1bit¤Ï̵»ë¤·¤Á¤ã¤¦¤è¤È¤¤¤¦warning¤é¤·¤¤¡£º£²ó¤Ï̵»ë¤·¤Æ¤âÌäÂê¤Ê¤µ¤½¤¦¤Ê¤Î¤Ç¤³¤Î¤Þ¤Þ¤Ë¤·¤Æ¤ª¤¯¡£


2012/08/08(Wed)

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¥ê¥»¥Ã¥ÈÆþÎϤÏñ½ã¤ËRST_N¤Î¿®¹æ¤ËLow¤òÍ¿¤¨¤ì¤Ð¥ê¥»¥Ã¥È¤¬¤«¤«¤ë¤È»×¤Ã¤Æ¤¤¤¿¤¬¡¢½ÅÍפʤΤϼ¡¤Ë¤Þ¤¿High¤Î¾õÂÖ¤ËÌ᤹¤³¤È¤À¤Ã¤¿¡£Á°²ó¤ÏRST_N¤òLow¤Ë¤·¤¿¤Þ¤Þ¥¯¥í¥Ã¥¯¤òÍ¿¤¨Â³¤±¤Æ¡¢DCM¤«¤é½Ð¤Ê¤¤½Ð¤Ê¤¤¤È¤¤¤¦¾õÂ֤ˤʤäƤ¤¤¿¡£¼Âµ¡¤Ç¤âÆ°ºî³Îǧ¡£

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DCM¤Ç25MHz¤Î¥¯¥í¥Ã¥¯¤ÎÀ¸À®¤Ï¤Ç¤­¤¿¤¬¡¢¥ª¥·¥í¤Ç¸«¤ë¤ÈÇÈ·Á¤¬¤À¤¤¤ÖÏĤó¤Ç¤¤¤¿¡£
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25MHz¤Ç¶îÆ°¤¹¤ë½ÐÎÏ¥Ô¥ó¤Ë°Ê²¼¤Îµ­½Ò¤òÄɲá£

NET "VGA_CLK_25M" PERIOD = 40.0ns HIGH 50%;

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2012/08/07(Tue)

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²ò·è¢ª2012/08/08(Wed)


2012/08/02(Thu)

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º£²ó¤ÎVision Chip¤Î¥·¥¹¥Æ¥à¤Ç¤Ï²èÁü½èÍý·Ï¤Ï¥«¥á¥é¤«¤é¤â¤é¤¦40MHz¡¢¤½¤ì°Ê³°(VGA½ÐÎÏ¡¢UART¡¢etc)¤Ï¥ª¥ó¥Ü¡¼¥É¤Î48MHzÊդ꤫¤é¼è¤ë¤ÈÎɤ¤¡£
¶ð¼¤µ¤ó¤Î¥·¥¹¥Æ¥à¤Ç¤Ï¥«¥á¥é¤Î40MHz¡¢¥ª¥ó¥Ü¡¼¥É¤Î48MHz¡¢18.432MHz¤Î3·ÏÅý¤ò»ÈÍѤ·¤Æ¤¤¤¿¡£
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18.432MHz¤È¤¤¤¦¥¯¥í¥Ã¥¯¤Î¿ôÃÍ

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ex) (18.432 * 10^6) / 9600 = 1920, 1920 / 96 = 20

DCM(Digital Clock Manager)¤ÎÀßÄê

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(»²¹Í)¶ð¼¤µ¤ó¤Î48MHz¤«¤é50MHz¥¯¥í¥Ã¥¯¤ÎÀ¸À®¥Ñ¥é¥á¡¼¥¿

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CLKIN Source¤Ï¥Ü¡¼¥É¾å¤Î48MHz¤À¤«¤éExternal¤«¤È»×¤Ã¤¿¤¬¡¢¶ð¼¤µ¤ó¤ÏInternal¤Ë¤·¤Æ¤¤¤ë¡£»ÅÍͽñ¤ò¸«¤ë¤È°Ê²¼¤Î¤è¤¦¤Ë¤¢¤ë¡£

Spartan-3¤ÎDCM»ÅÍͽñ : http://japan.xilinx.com/support/documentation/application_notes/j_xapp462.pdf
CLKIN¤òIBUFG¥°¥í¡¼¥Ð¥ë¥Ð¥Ã¥Õ¥¡ÆþÎÏ¥×¥ê¥ß¥Æ¥£¥Ö¤ËÀܳ¤¹¤ë¾ì¹ç¤Ï[External]¡¢¤½¤Î¾¤Î¥½¡¼¥¹¤ËÀܳ¤¹¤ë¾ì¹ç¤Ï[Internal]


2012/07/31(Tue)

Evernote¤¬Ëè²óƱ´ü¤Ë¼ºÇÔ¤¹¤ë

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¥½¥Õ¥ÈºÆµ¯Æ°¡¢MacºÆµ¯Æ°¡¢EvernoteÆþ¤ìľ¤·¤ò¤·¤Æ¤â¸ú²Ì¤Ê¤·¡£

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2012-07-31 15:54:57 sync [ENSyncEngine] ERROR:   exception adding note '¾ðÊóÄÌ¿®¤È´íµ¡´ÉÍýÆÃÏÀ 2012ǯÅÙÁ°´ü' to server
2012-07-31 15:54:57 sync [ENSyncEngine] ERROR: Sync exception: EDAMUserException(errorCode:5,parameter:"Data.body")

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2012/07/25(Wed)

FPGA(VIRTEX4)¤òÆ°¤«¤·¤¿¤È¤­¤Î¥á¥â

FPGA¤Ç¤Î´Êñ¤ÊÆ°ºî³Îǧ¤ËÀ®¸ù
¥Ü¡¼¥É : XCM-202A
VIRTEX4 XC4VLX160

outTes120627¤Çºî¶È

¥á¥¤¥ó¤ÎVerilog HDL

module outTes120627(IN_I, OUT_O);
    input IN_I;
    output OUT_O;

    assign OUT_O = IN_I;
endmodule


À©Ìó¥Õ¥¡¥¤¥ë

NET "IN_I" LOC = AK12;
NET "OUT_O" LOC = AJ12;

#NET "IN_I" IOSTANDARD = "LVCMOS";
#NET "OUT_O" IOSTANDARD = "LVCMOS";


LVCMOS¤Î¤òÍ­¸ú¤Ë¤·¤¿¤é¥¨¥é¡¼½Ð¤Æ¥³¥á¥ó¥È¥¢¥¦¥È¤·¤¿¤±¤É¡¢ISE¤Ç¤Þ¤È¤á¤¿¸å¤Ë¥Ô¥ó³äÉդΥì¥Ý¡¼¥È¸«¤¿¤éLVCMOS¤Ë¤Ê¤Ã¤Æ¤¿¡£¥Ç¥Õ¥©¥ë¥È¤À¤È¤³¤¦¤Ê¤ë¡©
»²¹Í : http://www.kumikomi.net/archives/2009/05/ioledrs-232.php

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2012/06/25(Mon)

FPGA¥Ü¡¼¥É(XCM-202)JTAG¥³¥Í¥¯¥¿

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2012/06/22(Fri)

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2012/06/05(Tue)

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