`timescale 1ns/1ns module count2-test; reg c, rst; wire [1:0] x; count2 count2(c, rst, x); initial begin rst = 0; #10; rst = 1; #10; rst = 0; #1000; $finish(2); end always begin c = 0; #100; c = 1; #100; end initial begin $monitor($time,,"rst=%b c=%b x=%b", rst, c, x); end endmodule