`timescale 1ns/1ns module fsm2-test; reg c, i, rst; wire x; fsm2 fsm2(c, i, x, rst); initial begin rst = 0; #10; rst = 1; #10; rst = 0; #1000; $finish(2); end initial begin i = 0; #500; i = 1; end always begin c = 0; #100; c = 1; #100; end initial begin $monitor($time,,"rst=%b c=%b i=%b x=%b", rst, c, i, x); end endmodule