use IEEE.STD_LOGIC_SIGNED.ALL;
トップ階層のtimer_topは、以下を参考に。 ※微妙にトラップが張ってあるので、内容をよく理解し、 間違いがあれば修正しながらながら入力すること。 また入力信号とスイッチとの対応は自分で決めたものを記述すること。
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity timer_top is port ( SW: in std_logic_vector(7 downto 0); LED: out std_logic_vector(7 downto 0); CLK50M: in std_logic ); end timer_top; architecture Behavioral of timer_top is component div1s port ( clk_i, rst : in std_logic; clk_o : out std_logic ); end component; component timer port ( clk, rst, set, run, s10, s60 : in std_logic; done : out std_logic; cnt : out std_logic_vector(11 downto 0) ); end component; signal rst, clk1s, set, run, s10, s60, done : std_logic; signal q : std_logic_vector(11 downto 0); begin set <= ... run <= ... s10 <= ... s60 <= ... rst <= ... LED <= ... itimer : timer port map(clk1s, rst, set, run, s10, s60, done, q); idiv : div1s port map(clk_i=>CLK50M, rst=>rst, clk_o=>clk1s); end Behavioral;
entity control is port( clk, rst, set, run, s10, s60, done: in std_logic; p10, p60, m1: out std_logic state_out : out std_logic_vector(1 downto 0) -- appended ); end control; ... process (state) begin case state is when IDLE_ST => state_out <= "00"; when SET_ST => state_out <= "01"; when RUN_ST => state_out <= "10"; when DONE_ST => state_out <= "11"; end case; end process; ...